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2N2/15 CW Transceiver Design Page

Section 1
Background - I've decided to design a new CW transceiver using some of the same design concepts employed in the highly successful 2N2/40 transceiver.  The design goal of this rig is to provide a 15 meter CW rig that has good performance, while using discrete, readily available components whenever possible, including the venerable 2N2222 transistor, so that the rig can be reproduced in 3rd world countries by ham radio operators of modest means.

Part of what is driving the desire to do this rig is the tremendous feedback I've received from hams worldwide, praising the simplicity and ease of construction of the 2N2/40 relative to its performance.  I'm hoping to extend what was learned in doing the 2N2/40 to this new rig.  The other driver is the current condition of the higher frequency bands with the sun spots perhaps a year or so from their peak, and the continuing good propagation for the next several years.

I've decided to use the internet as a learning platform and teaching tool.  My plan is to post all of the design, modeling, building, and testing information that is created as the 2N2/15 takes shape here on this part of my web page.  I'll also couple that with as much dialog as I can stand to write, given the other projects that I'm committed to doing.  Besides, you'll probably tire of reading it.  As we go on, hopefully the dialog will reduce, being replaced by more diagrams and pictures.

Copyright Notice - While I'm willing to share this experience with everyone, I expect you to respect the fact that the entire content of my web pages is copyrighted material.  That means that I own it, and you can't reuse it in any publication, nor commercial venture, etc. without my written approval.  That also means I own the design, and you can't kit it, nor sell it in any form, without my written permission.

Let the fun begin - by starting with what has already been completed on the design.

Several hours were spent looking at receiver geometries, that is, ways that a signal at 21 MHz, could be down converted to an intermediate frequency, amplified, filtered, detected, and amplified again as audio, and sent to a speaker.  One of the key drivers in this quest was the desire to use crystal frequencies that are readily available, in places other than the United States.  The first decision was that the intermediate frequency should be at 4.433 MHz, the European/Far East PAL color burst frequency.  The thinking here is that crystals at that frequency should be available in defunct television sets, and maybe at local television repair shops, or perhaps the equivalent of our Radio Shack stores.  However, selecting a relative low frequency for the i.f.. eliminates the possibility of also using a low frequency VFO to directly mix with the incoming r.f. to get the i.f. frequency, as was done in the 2N2/40.  Here is a diagram showing how that worked in the 2N2/40, for reference.

Another decision already made is that the VFO will operate around 2 MHz.  The reason for this is the success of the 2N2/40 VFO, with its low phase noise and great stability, both short term and long term.  This decision, and the previous one, then reduce the number of possibilities for frequency mixing to arrive at a workable design.  It may sound like a contradiction with the information presented in the previous paragraph, but it isn't.  What is missing is yet another element that works with the VFO to create a VFO signal at the required frequency, so that we can mix with the incoming signals on 15 meters, (21 MHz nominally) and still have an i.f. at 4.433 MHz.

This transformation could be accomplished in several ways, but I've already chosen the candidate method, another decision.  First, we are going to mix the VFO with a higher frequency to move it up to the required range.  That range is found by subtracting the frequency for the i.f., from that of the incoming 15 meter signal.  If the starting point is the low end of the CW band, that's 21.000 MHz.  Therefore, the required VFO signal that has a low end frequency of 21.000 - 4.433 = 16.567 MHz.  If the 2N2/15 is to be usable by the largest number of hams, we want it to cover all of the  U.S. CW band, that is, up to 21.200 MHz.  So the high end frequency VFO signal needs to be at 21.200 - 4.433 = 16.767 MHz.  That amount of coverage could be obtained two ways, either by having the VFO cover 200 KHz, or having it cover 100 KHz, and multiplying the output frequency by 2.  I'd rather keep the VFO range small, so that the output remains constant, and do the 2 times multiply.  So we have yet another, and final decision on creating the VFO section of the rig.  The only detail not yet revealed is what must the "higher frequency" be which was alluded too earlier.  That choice is a bit unclear, but only because of lack of knowledge of what higher frequency crystals might be more readily available in far off places.  My first choice, and the candidate so far chosen, is to make it 12 MHz.  That crystal frequency is available from virtually every crystal source available in the United States.  Using 12 MHz as the mixing frequency with the VFO times 2, we can determine the actual VFO frequency coverage.  The lowest actual VFO frequency is 16.567 - 12.000 = 4.567 MHz, which we then need to divide by 2, so we have 2.2835 MHz.  For the upper end, we have 16.767 - 12.000 = 4.767 MHz, again divided by 2, to get 2.3835 MHz.

There are several important points to be made here, before going on.  First, notice that the times 2 VFO signal is more than 100 KHz above the i.f. frequency.  This was done on purpose, so that we don't have the VFO signal landing in the i.f. as the VFO covers the required frequency range.  Second, this is just the first pass through a candidate VFO system.  Before finalizing this group of decisions, we need to do some rigorous analysis to see where all of the higher order mixing products fall.  We don't want any of them in the pass band of the input, nor the i.f.  If any of them do, we may need to modify the design appropriately, by either changing the 12 MHz mixing frequency, or shifting the VFO, or both.  It might even require changing the i.f. frequency chosen.

The VFO is revealed - in this block diagram.  You'll notice that it matches the description above.  The only elements not detailed were the band pass filter, and the amplifier.

The band pass filter is there to clean up the output from the mixer.  If you remember, when we mix two signals, we get their sum and difference,  and in reality, a lot more products representing some of the harmonics of the input signals, also mixed together.  A bit farther down the page, I'll show you the frequency response of this proposed filter, and we'll see the effect it has on the non desired mixing products.

The amplifier is there to boost the final signal up to the level that we need for the mixers, nominally +7 dBm.  This level corresponds to an rms voltage of roughly 0.5 volts.  A signal at that level is required to drive the diodes into saturation in the single and double balanced mixers that the proposed design will use.  More on those mixers later.

The VFO is revised - based on some feedback from Sly Liew, 9M8SL.  He commented that 12 MHz crystals are not as easy to come by as 14.318 MHz and 24 MHz crystals, from defunct computer I/O cards.  So, the possibility of using 14.318 MHz as the frequency for the LO in the VFO/Mixer combo was investigated, and it looks like that combination will work quite well.  The only give up will be having the VFO actually tune 100 KHz, and multiplying it.  With the 14.318 MHz LO, there is no need to do that, but instead, have the VFO tune 200 KHz directly.  That's not a really big deal, we'll just have to make sure the output stays reasonably constant over that range.  We are going to trade a X2 multiplier stage for a wider span in the VFO itself.  Not an unreasonable tradeoff.  So another decision has been made on the 2N2/15 design.

Just for completeness, I thought about using the 24 MHz crystal that Sly said was also available.  It could have been used with the original configuration, by adding a divider after the oscillator, so that we had 12 MHz for the LO signal.  However, I felt the added complexity of the additional divider was not warranted.

Earlier, I showed some calculations relating the VFO low and high end frequency coverage using 12 MHz as the local oscillator.  Those now need to be updated, with the change to the 14.318 MHz LO.  Here's what we get with the new LO frequency.  The lowest actual VFO frequency is 16.567 - 14.318 = 2.249 MHz.  For the upper end, we have 16.767 - 14.318 = 2.449 MHz.  The total band spread covered by the tunable part of this design is now 200 KHz.

Here is the revised VFO block diagram.  Some important information has been included on this diagram which is a table of the spurious outputs from the mixer, given the VFO frequency range, and the LO frequency.  As a result of running this analysis and seeing which harmonics of the VFO and LO potentially will cause a problem, low pass filters have been added between each of these signal sources and the mixer to minimize these higher order mixer products.  The spurious output analysis was done with the "SPURTUNE" program which came with Wes Hayward, W7ZOI's "Introduction to Radio Frequency Design."  By the way, this text and his "Solid State Design for the Radio Amateur", are two of my "must have" electronic design reference books.  What the spurtune program does is look at all of the outputs that will occur when mixing two frequency ranges, considering all of the harmonics of these two sources through their 15th harmonics.

Hopefully, we've arrived at the final configuration of the VFO.  If not, I'll add more to this area if the basic design changes significantly.

The next step will be to figure out the details of each box shown in the block diagram, starting with the VFO itself.  That should be reasonably straight forward since it will be copied from the 2N2/40 VFO.  Details will be forthcoming........

Receive and Transmit Block Diagrams - have already been fleshed out to some degree, based on some of the content the transceiver ought to have.  Here is what the receive strip looks like, and its companion transmit strip.  Both of these are subject to change, based on feedback, and other ideas that happen along.  Discussion of these block diagrams will also be forthcoming, but I thought everyone might like to get a first glimpse of the complete rig.

Section 2

VFO Details and Discussion
- gets underway here.  Sorry for the somewhat long delay, but I've refined the VFO design a little bit here and there, along with building up a prototype, just to make sure that it will work as intended.  An alternative design was also developed that does not use a 10 turn potentiometer for tuning, as that part may be too expensive or unavailable in some parts of the world.  So there will be two ways of building the VFO, one using a 10 turn potentiometer, and the other using a one turn potentiometer, with provisions for tuning multiple 20 KHz segments of the band.  This is the schematic of the version with the 10 turn potentiometer.  This is a complete VFO schematic showing all of the sections.  Please note that various key voltages are indicated as are signal location points.  As we go along, the signals at locations "A" through "N" will be shown and discussed.  Some of these signals are standard oscilloscope pictures, and others are spectral plots, which show harmonic and mixing details.  The alternative VFO design, which uses the single turn potentiometer, only includes those portions which are different from the main design.  That alternative design is shown here.

I had not really intended on building any of the 2N2/15 prior to starting on the real rig, but there were questions in my mind whether the VFO would be adequate, and I also didn't have a very good feeling regarding how much space would be required, due to its complexity.  So a decision was made to build the VFO portion and along the way, try to illustrate some on the design ideas employed, show some of the SPICE modeling used to validate the design decisions, and photograph the construction as it progressed.  All of that has been done to this point, with the VFO fully constructed.  Some of the parts are not those envisioned in the final version, but at the moment, some of the molded inductors needed in the diplexer are not available in my parts supply.  In fact, inductors L3, L4, and L5 are either air wound, or wound on T25-2 toroid cores.  With that, let's get started with is discussion of the VFO diagram, and see some pictures.

This VFO is tuned with a device called a varicap diode.  The decision to use a varicap instead of a conventional variable capacitor was due to the scarcity of suitable variable capacitors these days.  The diode used, an MVAM108, changes its capacitance as the reverse bias on it changes.  If the tuning voltage on an MVAM108 covers the range of 1 volt to 5.5 volts, the diode exhibits a capacitance change from about 500 pF down to 75 pF.  You'll notice on this chart that the voltage-capacitance curve is a straight line if it is plotted on semi-log graph paper.  However, the capacitance versus voltage isn't linear at all, but rather follows the equation that I've written at the bottom of the chart.  X is the amount of voltage across the diode, and Ct is the resulting capacitance.  A recent discovery relating to MVAM108 varicaps is that Toshiba makes a similar unit, a 1SV149, designed for AM radio tuning, as was the MVAM108.  A second discovery was that there are second sources for the MVAM108, now that Motorola no longer manufacturers this part.

One of the important aspects of having a stable VFO when using varicap tuning, is to have a well regulated supply for the tuning voltage.  That is accomplished in the VFO by using a Zener diode to supply the voltage not only for tuning, but also for Q1 which is a Colpitts type oscillator.  We'll detail that a bit later on.  The power supply for these two elements is comprised of resistor R1 and diodes D1 through D3.  D1 is a 5.1 volt Zener, and chosen because of its availability.  However, the oscillator needs a bit more voltage than the Zener could supply directly, so two common 1N400X diodes have been added in series to gain another 1.4 volts.  With this arrangement, we would expect test point V1 to be at 6.5 volts, and the prototype VFO measures 6.51.  That's good!  For those interested, the value of R1 was chosen so that the current flowing through the Zener would be at least 10 milliamps higher than the current required to run the rest of the circuitry.  That ensures that we are into the portion of the Zener's V-I curve where there is little change in voltage for a moderate change in current.  That's how we get decent voltage regulation.  If you do the math, supply voltage minus Zener voltage plus two diode drops, that gives 13.8 minus 6.5 equals 7.3 volts.  Dividing that by 390 ohms gives a current flowing in the Zener of almost 19 milliamps.  That amount leaves plenty to run the Colpitts oscillator, about 3 milliamps, and some headroom so that we keep above the 10 milliamp minimum when the supply voltage goes down to a lower value.  How do we know what the lower supply voltage can go to and still be in regulation?  You find that by computing the voltage drop across resistor R1 with 13 milliamps flowing through it, or a value of nominally 5 volts.  Add to that the drop across the Zener/two diode string of 6.5 volts, and we have the answer, it's 11.5 volts.  That's plenty of headroom for most line powered supplies, but if we were to run off of a gel cell, which could easily go down to 10 volts, we would want to reduce the value of R1.  The tradeoff is that we waste more power when the rig is running on a 13.8 volt supply.

The other important consideration in our power supply is using the junction between diodes D2 and D3 as the lower voltage reference for the potentiometer that supplies bias voltage to the varicap diode.  Ideally, the lowest we should go according to the MVAM108 chart is 1 volt, but we'll cheat just a little and go to 0.7 volts.  That will give us about 550 pF of capacitance.  Referring to the MVAM108 chart again, we can see that the highest voltage we probably want to have on the varicap is about 5.3 volts, since greater than that takes us away from the portion of the curve that fits our equation.  At 5.3 volts, we have about 80 pF of capacitance.  Resistor R2 provides the necessary voltage drop to have the top end of POT1 at 5.3 volts.   As an exercise, see if you can compute the value for R2.  I'll show that math a bit later on.  In my original design for this part of the circuitry, I had another pair of diodes in series where R2 is used to provide this drop.  When I got that portion of the VFO built, it dawned on me that the current demands for the POT1 circuitry were constant, so a simple voltage divider was sufficient.  If the alternative design is used, they those diodes will replace resistor R2.  1N4148 type diodes will suffice, as the current demands are low.

Here are some early pictures of this part of the VFO.  This one shows the first two pads mounted.  When  building Manhattan Style projects, I always seem to start in the  upper left corner of the board.  Someday, maybe I can get out of the rut!  Next is a picture showing the power supply.  The abandoned diodes are clearly seen in the upper right area.

Before going on, a few comments on the next several parts that are used.  R2 is there to help make the tuning linear, within limits.  Those limits are that were have the low end of the band at one end of POT1, the upper end at the other end of POT1, and the center of the band at exactly 5 turns.  While R2 is shown as 120K, we will find the correct value when the VFO is done by setting POT1 at 5 turns, and selecting a resistor that will put the center of the tuning range where the potentiometer is set.  R3 isolates the tuning voltage supply from r.f. energy that is on the varicap diode.  Capacitor C3 is one of many bypass capacitors used to keep r.f. energy out of areas where it is unwanted.

Transistor Q1 and its circuitry comprise a Colpitts oscillator.  Without going into a lot of detail about this oscillator, there are several points that will help one understand how it functions.  First off, the steady state biasing is fairly straightforward.  The supply for this stage is at 6.5 volts.  The principle reason for running this stage at a low voltage is to keep the r.f. currents in the capacitors and inductors as low as possible.  Doing so aids in frequency stability by keeping r.f. heating to a minimum.  Bias resistors R5 and R6 are selected to provide 1/2 the supply voltage plus about 0.7 volts, the amount that will be lost across the base-emitter junction.  The values shown place the base at 3.9 volts, resulting in the emitter being at 3.2 volts, or about half the supply voltage.  Having the emitter at 1/2 the supply allows the largest signal swings without going into a cutoff or saturated condition.  The emitter resistor, R7, is chosen to set a reasonable amount of quiescent current through the transistor.  I picked a value of 1K, which gives a bit over 3 milliamps of current, and is a common, easy to find value.

Capacitors C8 and C9 provide the feedback required to sustain oscillation.  From experience, the values shown were picked, with C8 having a reactance of about 70 ohms at the center of the VFO frequency i.e. 2.349 MHz.  Most oscillators of this type will operate with a very wide range of capacitor values.  The actual frequency of oscillation is controlled by all of the capacitors and the inductor, L1, shown back to the varicap diode, D4.  What may not be obvious is how each contributes, and explaining it isn't easy, but here is an attempt.  The basic frequency is determined by inductor L1, in parallel with capacitors C5, C6, and Cp, and follows the basic formula F=1/2*pi*sqr(LC) where L is the inductance of L1, 8.1 uH and C is the combined capacitance of C5, C6, and Cp, about 390 pF.  Adding to the capacitance supplied by C5, C6, and Cp, is that of the varicap diode D4, which is in series with capacitor C4.  At minimum D4 capacitance, we have 80 pF in series with 330 pF, which is about 64 pF.  (Remember, capacitors in series always result in a total capacitance less than the smallest capacitor)  At maximum D4 capacitance, we have 550 pF in series with 330 pF, for a total of about 206 pF.  So varicap diode D4 supplies a total capacitance change of about 140 pF.  The last set of capacitors which determine where the VFO will oscillate are from the series combination of C7, C8, and C9.  This series combination also is in parallel with C5, C6, and Cp, and contributes an additional 40 pF of capacitance.  With the values shown, the VFO tunes from about 2.249 MHz to 2.452 MHz, or just slightly over 200 KHz.  The tuning span is basically controlled by the voltage swing on D4, and the coupling due to capacitor C4.  C5 principally controls the coupling of the resonant elements to the rest of the circuit, and is the most critical element.  Too small a value here results in the oscillator not starting.  Too large results in a reduced tuning range, and stability problems due to excessive r.f. heating.

Here are some more pictures showing the VFO built up through Q1.  This picture shows the varicap diode and coupling capacitor C4.  A trimmer was used in parallel with C4, but that was scrapped due to frequency stability problems from r.f. heating in the trimmer. A second trimmer was used as part of the parallel tuning across L1.  That's shown in this picture.  It too was scrapped due to stability problems.  After those trimmers were removed, this is what the VFO up through transistor Q1 looked like.  At this point, the VFO would operate and the output could be viewed on an oscilloscope, connected to the emitter of Q1.

This is a good time to present the first series of oscilloscope traces and spectral plots showing what the signals look like at points "A" through "C".  The first picture is at point "A", which is the "hot" end of inductor L1.  Notice the amount of signal swing, nearly 10 volts peak-to-peak, and very sinusoidal.  The next is an oscilloscope picture taken at point "B", the base of Q1.  Distortion seen in this waveform is due to dynamic impedance changes occurring in the base-emitter junction during a single cycle.  This is the waveform at point "C", the emitter of Q1.  Also, a spectral plot at "C" showing the fundamental frequency (2.349 MHz) and harmonics of the oscillator out to the 8th one.  This is quite typical of any VFO (or oscillators in general) before cleaning up the signal with additional tuned circuits.

Signal from the emitter of Q1 is coupled to the buffer amplifier, Q2.  Q2 operates as an emitter follower, and as such, has a voltage gain a bit less than 1, but a fair amount of current gain, nearly 200 at dc conditions.  In fact, this can be confirmed by dividing the emitter current by the base current.  The base current is the drop across R8, 0.5 volts, divided by 4.7K ohms, for a current of 106 microamps.  The emitter current is the voltage drop across R10, 2.0 volts, divided by 100 ohms, or 20 milliamps.  Dividing the emitter current by the base current shows a dc gain of 188.

The coupling between stages is done with resistor R8, which supplies the operating bias for Q2, and also couples the signal from oscillator Q1.  It also provided a small amount of isolation due to its size, but most of the isolation comes from the base resistance of Q2, which is about 24.4 K ohms (Vb divided by Ib) plus the effective impedance of emitter resistor R10 being multiplied by the ac gain of transistor Q2, which is about 100.  This gain value is derived from the Ft of the PN2222, which is 250 MHz, divided by the frequency being amplified, which is nominally 2.5 MHz.  The input impedance seen by Q1 is then 4.7K + 24.4K + 10K ohms for a total of about 39K ohms.  This is the waveform at point "D", the emitter of Q2.  It doesn't look a lot different than the signal at the emitter of Q1, except for being somewhat smaller in amplitude.  Here is a picture of the VFO construction through the Q2 stage.  Some values have changed, since this photo was taken, to improve performance.

From the emitter of Q2, the signal passes through a 3 element low pass filter, which also has the inductor tuned to parallel resonance at the second harmonic of the VFO center frequency, nominally 4.7 MHz.  This resonance adds a deep null to the frequency response of the filter, and also improves the frequency response rolloff of the filter at higher frequencies.  This helps to suppress the second  and higher order harmonics, so that they don't get into the mixer.  The values used in the filter are for an input impedance of 25 ohms, and an output impedance of 50 ohms.  These values were chosen since the measured output impedance of Q2 was about 30 ohms, and expected to be lower with the stiffer load imposed by the mixer.  Here is a computer model of the filter used, and its theoretical frequency response.  Note the deep null at 4.7 MHz which was described earlier.  Before leaving this section, let's have a look at the signal at point "E", to see the effects of the low pass filter.  This is the waveform at point "E".  Note the waveform is now more sinusoidal.  The distortion seen is actually from the effects of driving the mixer, and the non-linear characteristics of the diodes being reflected back.  Here is the spectral plot of the same point.  Notice the significant reduction in the harmonics now that the signal has been passed through the filter.

The next step was to build the double balanced mixer stage, and get it working correctly.  This mixer used broadband transformers, trifilar wound on type 43 ferrite T37 size cores.  The wires used are #30 gage, and three strands of wire were wound together until there was about 8 twists per inch of length.  While no extensive tests were performed, the transformers seemed to be well balanced on the diode windings.  Diodes D5 through D8 were electrically matched by measuring the forward voltage drop across each diode while supplying current through the diode via a 1K ohm resistor, sourced from a stable 13.8 volt supply.  Here is a picture of the VFO with the DBM built up.  Some of the capacitors on the input side of the input low pass filter have been changed as the design of that filter evolved.  On the output port of the DBM is a 51 ohm resistor at this point in the construction.  The local oscillator port (LO port), has a vertical wire soldered to it so that it could be driven with a signal generator for testing, since at this time, the 14.318 MHz local oscillator had not been constructed.  Before leaving this part of the circuitry, it is instructive to look at the waveform of point "F".  The small frequency ripples seen on the peaks of the main sinewaves is from the LO signal.  These ripples are caused by small imbalances in the dynamic charactistics of the statically matched 1N4148 diodes.  Looking at point "J", we see the product of the LO signal and the lower frequency VFO signal.  When we look at the output of the mixer, point "K", the lower frequency VFO signal is greatly attenuated, as is the LO signal, and the predominant components are the sum and difference of these two.  That's not completely obvious in the oscilloscope trace, but certainly is in this spectrum plot of the same point.  The first peak is the VFO, the two very large peaks and the difference and sum signals, and in between them is the LO signal.  All of the other signals going out to nearly 250 MHz are various unwanted mixing products that always occur with any good mixer.  The role of the diplexer on the output of the mixer is to pass on the desired signals to down stream circuits, while attenuating the undesired products, while also keeping the termination on the mixer output port at a constant impedance.  The diplexer circuitry will be discussed in detail farther down the page.

After this much of the circuitry was built and tested, it was time to build the 14.318 MHz local oscillator part of the VFO.  The oscillator is another Colpitts, feeding into a low pass filter to remove the higher order harmonics.  On the output of the double balanced mixer can be seen the diplexer that properly terminates it, and removes undesired mixing products.  Here is another picture showing the construction to that point.  Removing the LO harmonics makes the job of cleaning up the output of the mixer easier, since these signals are highly attenuated.  This low pass filter is designed for 200 ohm on the input side, which is approximately the output impedance of the oscillator.  On the output side of the filter, the impedance is set for 50 ohms so that the mixer r.f. LO port is properly terminated.  Shown here is a computer model of the LO low pass filter, along with its frequency response.  This oscilloscope trace is at point "H", the emitter of local oscillator transistor Q3.  The spectrum at point "H" shows many harmonics, again typical of all untuned crystal oscillators.  On the other side of the LO low pass filter, the spectrum of point "I", the harmonic content would be dramatically reduced if it were not for reflections coming back from the DBM, and distortion due to driving the mixing diodes into conduction.  However, the even harmonics are nicely attenuated, as predicted by DBM theory.

The diplexer on the output of the DBM uses a common band pass/band pass design.  The first band pass filter is composed of elements C16 and L3, which have a parallel resonance at 16.667 MHz, the center of the VFO output range.  Output from the mixer in this frequency band is unattenuated, as the parallel combination represents a high impedance.  Out of band signals see a lower impedance and are routed to ground through the 51 ohm resistor, R11.  In a similar manner, the second band pass filter, composed of elements TC1, C17 and L4, has a series resonance at 16.667 MHz.  In band signals are passed essentially unattenuated to load resistor R13.  Out of band signals are attenuated by either higher capacitive or inductive reactance, depending on the signal frequency.  Some comments are in order concerning the design of this diplexer.  My original configuration had all of the elements set at 50 ohms reactance for the two capacitors and the two inductors.  This configuration was also modeled.  From the model, it was clear that the diplexer was operating correctly, but that its ability to separate the desired inband signals from those out-of-band was marginal at best.  It became apparent that the parallel resonant LC needed reactances as small as possible, and the series LC needed to be as large as possible to offer optimal discrimination to unwanted signals, and still maintain an overall impedance of 50 ohms.  Further analysis led to the conclusion that the reactance values had to be scaled up and down from 50 ohms by the same constant.  The value of L3 was then chosen at 0.15uH, as this is the smallest value available for common molded inductors.  Its reactance value at 16.667 MHz was used to size capacitor C16.  The reactance of L3 was divided into 50 ohms, and this then became the scaling value for the reactances of the series resonant LC.  Interestingly, the fact that L3 is 1/10 the size of L4 is purely coincidental.  The other diplexer used in the 2N2/15 is already designed, and that relationship does not carry through.  Here is a closeup view of the diplexer after is was added to the substrate.  This is the model for the diplexer, and here is its frequency response.  Notice in the frequency response plot how constant the input impedance is for this design.  The input (red) trace shows no deviation from the -6 dB level from 1 MHz through 100 MHz.  The output from the diplexer section is shown in this oscilloscope trace for point "L".  The variation in amplitude is still due to the undesired, lower frequency component(s), the will be attenuated more in the output stage.  Here is the spectrum of point "L", which shows the improvement due to the diplexer.  Compare this spectrum plot to that of point "K".  Changing the resolution allows us to have a better look at points "K" and "L".

A tuned output amplifier completes the VFO section.   This amplifier is biased for class A operation, to minimize distortion of the output signal.  A 50 ohm load is presented to the diplexer by using a 51 ohm resistor as part of the bias string, but grounding the lower end for r.f. signal components.  The 6:1 ratio transformer in the collector steps down the output impedance to allow driving a 50 ohm load.  Power available from this stage is about +10 dBm, suitable for driving the Rx and Tx balanced mixers in the rest of the 2N2/15.  This is a picture of the VFO with this section added, and here is a closeup of the output stage.  The waveform at point "M", the collector of transistor Q4, and the spectrum plot that corresponds to that point, are shown here.  The amplitude variation is due to beating between the desired 16.667 MHz signal (LO+VFO), and the undesired 11.969 MHz signal (LO-VFO). And finally, here is point "N", the output waveform, and its corresponding spectrum plot.  The only signal component left besides the desired 16.667 MHz signal is the second harmonic of that frequency, and it is down 45 dB from the desired signal.  As an aside, this is a picture of the output transformer T3, to show how it was wound.  The primary and secondary were done as a single winding, with a long tap at the 24th turn.  That tap was later split apart, to produce the two independent windings, as shown in the picture.  The secondary was originally wound with 6 turns, but later two were removed to achieve the desired impedance transformation.

This completes the description of the VFO section.  When I go into the Rx and Tx strips, I'll try not to do this much building and testing without adding information to this web site.  It was not my intent to do the project that way, but rather in smaller packets of information for ease of understanding and ability to follow along -- The Management!

Section 3

Receive Strip
- The receive strip will start off with the T/R Switch, the first block shown on the Rx block diagram.  This section will begin by showing the SPICE model for the T/R switch that I'd like to use.  It is a variant of the W7EL series capacitor-series inductor that has been used in many qrp rigs because of its simplicity.  The 2N2/15 version is similar to that used in the NorCal 40, designed by N6KR.  In this version of the switch, the diodes are replaced with a low collector capacitance transistor, driven from the Tx control line.  This diagram, is the Electronic Workbench version of the circuit model.  It is  drawn so that the parts that will be carried over to the receiver are easy to identify.  Those parts include the 23pF capacitor, which in the built version, will be a trimmer, the 2.2uH inductor, the 0.01uF capacitor after the inductor, and the transistor and associated components, except for the switch and 13.8 volt dc source shown.  The switching function will be done by the Tx line in the rig.  The frequency generator and its 50 ohm source, and the 50 ohm load resistor are only elements needed for the simulation to be accurate, and run.  The next diagram, shows the frequency response at 4 key points.  Looking at the key, we see that the red trace is marked "Ref", and is actually the output of the frequency generator, which has an impedance of 0 ohms, so doesn't vary regardless of the load applied to it.  The blue trace is the input to the switch.  This signal is the junction of the 50 ohm input resistor and the 23pF capacitor.  Next is a green trace which is the junction of the 23pF capacitor, and the 2.2uH inductor, and forms the heart of the T/R switch, which will be explained in a moment.  Finally, the brown trace is the output of the switch, the signal appearing on the top of the 50 ohm load resistor.  Now about the "heart of the T/R switch" comment.  This switch works in part by passing signals that are at the series resonant point of a series connected capacitor and inductor on to the receiver input stage.  The inductor value was chosen to provide a relatively high impedance, while still allowing a resonating capacitance value that was not too small, to minimize distributed capacitance of the inductor to predominate.  In this case, a 2.2uH inductor was chosen as it has about 300 ohms of reactance at 21.1 MHz, the center of the 15 meter CW band.  The capacitor needed to tune this value of inductance to resonance is about 26pF.  The fact that the simulation uses a 23pF capacitor is only because of the added capacitance due to the PN2222 transistor connected to the node between the capacitor and inductor.  At resonance, the loss through the series capacitor-inductor combination is quite small, on the order of 1dB or less.  That can be seen by looking at the input and output traces, which differ in amplitude at resonance only by a small amount.  What is also interesting, and why I included this plot, is the voltage magnitude developed at the junction of the capacitor and inductor, the green plot.  You'll notice that the voltage here is roughly 6 times greater than the input or output voltage at resonance, the effect of going from a 50 ohm source impedance, to a 300 ohm reactance, and back down to a 50 ohm load impedance.  Put another way, the ratio of 50 ohms to 300 ohms, or 6 times.  This effect is important, as it helps determine the amount of attenuation that we can achieve through the T/R switch, when we are in the transmit mode.  The attenuation comes about by using the transistor during transmit to short the junction of the capacitor-inductor combination to ground during transmit.  When that happens, the reactances of these two elements no longer cancel each other, but become high impedances being driven by the input, and in series with the output load.  This next diagram shows the T/R switch in the receive mode, with the three traces being the reference, input and output.  Here, there is but about 1dB loss from input to output.  Now the transistor is turned on, and we can see what has happened in the transmit mode.  The input has changed substantially due the the high capacitive reactance, and the output is now attenuated by more than 55dB, far more than we need to protect the downstream input stages of the receiver.  Taking the junction of the capacitor-inductor pair to ground during transmit also places the capacitor of this pair in parallel with the first capacitor of the transmit output low pass filter.  So when we build that filter, we will need to subtract off about 25pF from whatever value we end up calculating, to account for this value.

The next step is to build this T/R switch, and then make some measurements on it.  Having done that, we'll compare the real world results to the computer model that was just presented.

T/R Switch construction and testing have been completed.  The building was done on the 5X7 inch PC board substrate that was prepared for this rig.  The area bordered by the blue line seen in the picture was to be the VFO area, but this line has been removed, as the VFO will require more space.  A chemical process was used to tin the copper, but the results are not very satisfactory.  The tin plate seems to vaporize during soldering, and the soldered connection looks less than optimal, so don't do that step on your rig.  This picture shows the T/R switch construction.  The input is at the front pad to which the trimmer capacitor is soldered.  Output comes off of the rear right pad to which a 51 ohm load has been soldered, so that measurements could be made.  The design shows a 2.2uH coil for the main inductor, but a 1.8uH was used because it was available.  Very little performance difference will result from this kind of change.  Notice the 1mH choke, collector resistor, and bypass capacitor are on the left side of the series tuned C/L pair.  This arrangement made it easy to add the transistor and base bias resistors to the right, and leave space for the first coil of the double tuned front-end filter which is the next stage to be done.  My equipment does not make it possible to fully duplicate the plots produced from the earlier computer modeling.  However, I did sweep the filter from 5 MHz to 50 MHz, and captured the input, junction between the C and L components, and the output.  On the plots, the 5 MHz point is the 1st division, and 50 MHz is at the 9th division.  This is the input plot.  It generally looks like the computer version, but it is obvious the circuit is responding a bit different than did the model, as consequence of components with real losses which are not comprehended in the simple model that was used.  Here is the junction plot, between the trimmer and the 1.8uH choke.  It looks quite good, and notice the scale is twice that of the input to keep the signal within the scopes range.  It isn't the 6 times multiple of the input signal like the modeling plot, but more like 2.75 times.  Some of the difference (small) is due to using a 1.8uH choke, but most of if is due to circuit losses, mainly in the inductor.  Here is the output plot.  Its about 5 dB lower than it should be, but by now you probably understand why - -  circuit losses again!  That loss will be made up in the r.f. amplifier stage.  The final two plots show the output only in the Rx mode, and the Tx mode, so we can see the effects to turning on the transistor.  In this first plot, the drive to the circuitry has been increased so we can see the attenuation a bit better in the second plot.  Notice the signal level is 1600 millivolts peak-to-peak.  The second plot shows the output with the transistor conducting.  We're now getting about 8 millivolts peak-to-peak.  That calculates out to 46 dB of attenuation, not as good as the computer model, but still quite sufficient.

That's it for the T/R Switch.  I hope you have followed the discussion, and learned a bit along the way.  The next installment will deal with the computer model and response plot for the Receiver Input Bandpass Filter.

The Receiver Input Bandpass Filter is a classic two resonator design with light coupling and very similar to those shown in Solid State Design for the Radio Amateur.  The design procedure given by the authors (Appendix 2) was followed, using 0.4 MHz as the desired -3 dB bandwidth.  The resulting filter was then constructed within EWB, and that model is shown here.  As can be seen, inductor losses are modeled as parallel resistors.  An unloaded Q of 200 was assumed.  The two 47pF capacitors shown will be 5-50pF trimmer capacitors, with perhaps some parallel capacitance, when this circuitry is constructed.  This plot is the frequency response of the filter, which is being swept from 17 to 25 MHz.  As can be seen, the -3dB bandwidth is very close to the 0.4 MHz design, and the insertion loss is nominally 4dB.  The actual filter will probably be worse than this due to circuit losses which this simplified model does not encompass.

Having just described the receive input filter, the next step was to add this filter to the output of the T/R switch.  This construction was completed, and some early testing revealed the combination did not work all that well together.  The basic problem was that the output of the T/R switch did not properly terminate the input of the bandpass filter, thereby leading to some rather strange passband characteristics.  The desired 0.4 MHz flat response could not be achieved, so the design of the T/R switch was changed a bit as shown in this diagram.  Essentially, the 22pF input capacitor, the 2.2uH inductor, and the 0.01uF output capacitor of the original T/R switch design were replaced with the 10pF input capacitor of the bandpass filter, but that capacitor was split into two parts, a 12pF and a 33pF unit.  That series combination, along with the parasitic collector capacitance of the 2N2222 transistor, give the required 10pF equivalent capacitance.  With those values, the passband of the filter is correct.  The T/R switch no longer exhibits any tuned characteristics, as these were eliminated when the inductor was removed.  Here is a frequency response plot of the T/R switch/input filter combo, with the T/R switch in the "receive" mode.  The corresponding plot with the T/R switch in the "transmit" mode is shown here.

New T/R Switch/Rx Input Filter construction and testing are described next.  The first part of the construction was to rip up the input circuitry of the old design, rearrange the remaining circuitry, then add the 12pF and 33pF capacitors of the new design.  Then the two inductors and their associated trimmer capacitors were added, along with the 10pF output coupling capacitor.  One of truely great features of Manhattan Style construction is to be able to change circuitry at will, without creating a lot of extra work. You remove the uneeded parts, pop off the pads that aren't needed or in the wrong place, and proceed with building the new circuitry.  Once these steps were completed, the substrate looked like this picture.

Only a few measurements have been taken at this point.  This plot shows the overall frequency response of the filter, in the "receive" mode.  The span of the plot is 10 MHz, with each division being 1 MHz, and centered at 21 MHz. This plot was produced by sweeping the input filter with a signal generator, and capturing the output on a digital oscilloscope (DSO).  Normally for a frequency response plot, the vertical scale would be logarithmic and calibrated in dB, but as can be seen, it is linear when measured with the DSO.  Further measurements of the filter indicate an overall loss from input to output of 14 dB.  This is quite a bit higher than the computer model predicts, but the computer model does not comprehend all of the circuit losses which occur in actual circuitry.  Most of the loss is probably in the inductors, with a smaller amount occuring in the capacitors.  One of the interesting aspects of measuring a filter such as this is the large effect on the filter from the DSO probe.  The probe has 14pF of capacitance, and significantly changes the response of the filter when connected to any of the interior nodes.  Only the low impedance end nodes, where it is driven and the terminating 50 ohm resistor, are suitable places for measuring.  Knowing that the loss through the filter is 14 dB gives some insight into how much gain the following r.f. amplifier stage should have.  At a minimum, it should be 14 dB, to make up for at least the filter loss, and probably a few dB more would be in order.  Something on the order of 15 to 20 dB ought to do a good job.  That's the next block that will be designed, modeled, and built.

The next installment will cover the design, modeling, and buildup of the r.f. amplifier block.

Receiver Input R.F. Amplifier design, modeling and construction are the next steps in this rig's evolution.  The actual form of r.f. amplifier used here is a duplicate of that in the output of the VFO section.  This r.f. amplifier has a very stable input impedance, due to the 51 ohm resistor in the input.  This was required to ensure that the input filter would be properly terminated at nominally 50 ohms.  In addition, this amplifier has plenty of gain, so that the input filter loss could be made up.  Another PN2222 transistor has been added to the basic amplifier design, to allow the gain to be varied from about +16 dB, down to -20 dB.  This r.f. amplifier will be controlled by the AGC, and its gain set by that loop, depending on the level of the input signal.  Also, we'll take advantage of this property, and reduce the gain to its minimum value during transmit by applying a positive bias signal into the control transistor base.

Shown here is the EWB computer model of this r.f. amplifier circuit.  The basic circuit is a tuned output amplifier, with the input signal developed across the 51 ohm resistor.  The lower end of this resistor is grounded for r.f. purposes.  However, the bias voltage is supplied from the 10K resistor and the 2.2K resistor to ground, with the 51 ohm resistor being part of the 2.2K resistor for bias purposes.  A T6-37 toroid with 16 primary turns and 2 secondary turns is in the collector of the PN2222 transistor.  The primary of the transformer is tuned to 21.1 MHz by the 52 pF capacitor shown in the diagram.  At the emitter, the two resistors of 39 plus 100 ohms set the queiscent current through the transistor to about 11 millamps.  Under full gain conditions, the second transistor has no bias voltage applied, therefore is cutoff, and does not supply any current through the 100 ohm resistor, which the transistors share.  This maximum gain condition is shown in this first frequency response plot.  The ref shown  (red trace) is the voltage of the signal source, which is by default, 0 ohms impedance.  Input to the amplifier (blue trace) is the voltage measure at the base of the first transistor.  And the output from the amplifier (green trace) is the voltage measure across the secondary of the transformer in the collector circuit.  The output voltage is also impressed across the 50 ohm load resistor, as can be seen in the diagram.  Applying voltage to the base of the second transistor causes it to start conducting.  When that happens, current from its emitter now flows into the 100 ohm resistor shared by both transistors.  As current from the second transistor increases, it decreases the flow of current through the first transistor, which is the amplifier, causing the gain to decrease.  At some bias point, virtually all of the current flowing into the 100 ohm resistor is from the second transistor.  When this condition is reached, the first transistor is not amplifying at all, and the signal level on the output is much below the level of the signal on the input.  That condition is shown in this second frequency response diagram.  Now we see the output about 20 dB below the input signal.  While this 35 dB range isn't extremely large, hopefully it will suffice to limit the input signals during receive, and protect the front-end of the receiver during transmit, with the help of the T/R switch that we've already seen.  The final plot available from the EWB analysis, is that of the transisient response of this amplifier.  I've included it so that you can see the linearity.  This plot was also used for determining the power gain of the amplifier.  If you use the input and output voltages shown, and remember these voltages are being developed across 50 ohms, see if you can calculate the power gain.  You should get a value of about 16.7 dB, based on this plot.

After this circuitry was modeled, it was added to the substrate.  This picture shows how the substrate looked with the r.f. amplifier added.  The 52 pF capacitor shown in the EWB model is the trimmer shown to the right of the T37-6 toroid transformer to the left in this picture.  Also, the second PN2222 which controls the gain is the leftmost of the pair toward the top-left edge of this view.  The output of the transformer is terminated with a 51 ohm resistor to allow for testing.

Testing this stage consists of driving the amplifier with a signal generator, which is  being swept from 10 MHz to 30 MHz,  and measuring the output with an r.f. probe attached to an oscilloscope.  Since the time to sweep across 20 MHz is somewhat long, using an oscilloscope with digital storage capability makes displaying the output waveform rather easy.  Shown here is the frequency response plot of the r.f. amplifier being swept over 20 MHz.  As can be seen, the tuning appears quite sharp, but most of that is due to the fact that the amplitude is plotted linearly, instead of dB, which is more common.  The 0 reference points and -3 dB, half power points are shown on the plot.  If this data were plotted using dB as the "Y" axis, the response would not look quite as "peaky".  This next plot was used to determine the gain of the r.f. amplifier, and consists of the input and output signal amplitudes displayed on the oscilloscope.  The driving frequency is 21.1 MHz, the center of the amplifier's passband.  Using the peak-to-peak signal amplitudes shown in this plot, one can calculate the gain to be 16.8 dB.  As an exercise, see if you can do that calculation.  This gain figure is within about 0.1 dB of that predicted by the EWB math model shown earlier.

The next step is to add the double balanced mixer to the output of the r.f. amplifier.  With that addition, we can hook the VFO to the LO port of the DBM, and use another receiver as the i.f. amplifier and detector, and hear signals on 15 meters.  We'll do that in the next installment.

In the meantime, the process of building a section, writing the technical documention for web publishing, doing the required measurements and pictures, etc. was really derailing my creative processes.  So I bypassed all of the above for a while, and completed the design and construction of the receiver portion of the rig.  Along the way, I took lots of pictures, made suitable notes of important details, and intend to go back and restart the section-by-section technical forum.  On a more positive note, there is now a complete set of schematics for the receive strip, and those are now available.  Selected pictures are also posted so you can see what the receive strip looks like, and I'll present some early performance measurement data.

2N2/15 Receive Strip Schematic Diagrams are available here

2N2/15 Receive Strip Construction Pictures

Front end through r.f. amplifier

Front-end, plus DBM, diplexer, and filter driver

Filter driver and main crystal filter

1st filter terminator, i.f. amplifier, roofing filter, and 2nd filter terminator

Product detector

Rx local oscillator and product detector

Upper two thirds of substrate populated

Audio amplifier, phase inverter, audio mute, and audio pre-amp

AGC amplifier

Complete receiver strip

Performance Data

I've only had a chance to make a few basic measurements on the receive strip, but initial results are very promising.  The rig has an MDS of -130 dBm, or 0.07 microvolts, for those who would prefer the number that way.  Obviously, plenty of sensitivity.  The other measurement that has been made is image rejection.  The image for this receiver is at 12.234 MHz, and is -95 dB down from the desired signal at 21.1 MHz.  For this measurement, the center of the receive passband was used. 

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